Write a SystemVerilog code for a priority encoder with 8 inputs.

Sure, here’s an example of a priority encoder with 8 inputs implemented using SystemVerilog:

module priority_encoder_8to3(
  input logic [7:0] in,
  output logic [2:0] out
);

  always_comb begin
    casez(in)
      8'b00000001: out = 3'b000;
      8'b00000010: out = 3'b001;
      8'b00000100: out = 3'b010;
      8'b00001000: out = 3'b011;
      8'b00010000: out = 3'b100;
      8'b00100000: out = 3'b101;
      8'b01000000: out = 3'b110;
      8'b10000000: out = 3'b111;
      default: out = 3'b000;
    endcase
  end

endmodule

In this code, we define a module called `priority_encoder_8to3` with two ports: `in` and `out`. The `in` input is an 8-bit binary input that represents priority signals, and the `out` output is a 3-bit binary output that represents the highest priority signal.

The `always_comb` block is used to describe the behavior of the priority encoder. The `casez` statement is used to specify the priority encoding logic for each combination of the input signals. In this case, the priority encoding is based on the most significant set bit in the input signal.

For example, if the input signal is `8’b00101100`, the output signal `out` will be `3’b011`. This represents the highest priority signal, which is the signal at position 5 (counting from 0) of the 8 possible input signals of the priority encoder.

Note that in this implementation, if multiple input signals are set to 1, the priority encoder will select the highest priority signal based on its position in the input signal. If no input signals are set to 1, the priority encoder will output an all-zero value.

You can instantiate this module in your top-level design hierarchy and connect it to other modules or input/output signals as needed.