Sure, here’s an example of a 4×16 decoder with active-low outputs implemented using SystemVerilog:
module decoder_4x16_active_low( input logic [3:0] in, output logic [15:0] out ); assign out =
(16’b0000000000000001 << in); endmodule
In this code, we define a module called `decoder_4x16_active_low` with two ports: `in` and `out`. The `in` input is a 4-bit binary input that represents the input selection, and the `out` output is a 16-bit binary output that represents the selected output with active-low logic. The `assign` statement assigns the output signal `out` the value of a bit-shifted binary number. The `<<` operator performs a left bit-shift operation by the number of bits specified by the input signal `in`. This results in a binary number with a single '1' bit at the corresponding position of the input selection, and all other bits set to '0'. The `
` operator is used to invert the value of the binary number, resulting in an active-low output signal. For example, if the `in` signal is `4'b0011`, the output signal `out` will be `16'b1110111111111111`. This represents the selected output of the fourth output line (counting from 0) of the 16 possible output lines of the 4x16 decoder with active-low logic.
You can instantiate this module in your top-level design hierarchy and connect it to other modules or input/output signals as needed.