Sure, here’s an example of a 4-bit shift register with left and right shift options implemented using SystemVerilog:
module shift_register_4bit(
input logic clk,
input logic [3:0] in,
input logic left_shift,
input logic right_shift,
output logic [3:0] out
);
always_ff @(posedge clk) begin
if (left_shift) begin
out <= {out[2:0], in[0]};
end
else if (right_shift) begin
out <= {in[3], out[3:1]};
end
end
endmodule
In this code, we define a module called `shift_register_4bit` with four ports: `clk`, `in`, `left_shift`, `right_shift`, and `out`. The `clk` input is used as the clock signal, the `in` input is a 4-bit binary input that represents the data to be loaded, the `left_shift` input is a control signal which shifts the data to the left when it is asserted, the `right_shift` input is a control signal which shifts the data to the right when it is asserted, and the `out` output is a 4-bit binary shift register that shifts the data based on the control signals.
The `always_ff` block is used to describe the behavior of the shift register. The `posedge clk` event triggers the shift register to shift the data on every rising edge of the clock signal.
When the `left_shift` signal is asserted (`left_shift = 1`), the shift register shifts the data to the left (`out <= {out[2:0], in[0]}`). This is achieved by concatenating the three least significant bits of the output signal (`out[2:0]`) with the least significant bit of the input signal (`in[0]`). When the `right_shift` signal is asserted (`right_shift = 1`), the shift register shifts the data to the right (`out <= {in[3], out[3:1]}`). This is achieved by concatenating the most significant bit of the input signal (`in[3]`) with the three most significant bits of the output signal (`out[3:1]`). If both `left_shift` and `right_shift` are deasserted, the shift register maintains its current value. You can instantiate this module in your top-level design hierarchy and connect it to other modules or input/output signals as needed. Note that you can modify the code to implement a bidirectional shift register by adding another control signal and modifying the logic in the always_ff block accordingly.