Sure, here’s an example of a 4-bit binary counter with asynchronous reset implemented using SystemVerilog:
module counter_4bit_async_reset(
input logic clk,
input logic reset,
output logic [3:0] count
);
always_ff @(posedge clk, negedge reset) begin
if (!reset) begin
count <= 4'b0000; // reset to zero
end
else begin
count <= count + 1; // increment count
end
end
endmodule
In this code, we define a module called `counter_4bit_async_reset` with three ports: `clk`, `reset`, and `count`. The `clk` input is used as the clock signal, the `reset` input is an asynchronous reset signal which resets the counter to zero when it is asserted, and the `count` output is a 4-bit binary counter that counts from 0 to 15.
The `always_ff` block is used to describe the behavior of the counter. The `posedge clk` event triggers the counter to increment on every rising edge of the clock signal. The `negedge reset` event triggers the counter to reset to zero on every falling edge of the reset signal.
When the reset signal is asserted (`reset = 0`), the counter is set to zero (`count <= 4'b0000`). When the reset signal is deasserted (`reset = 1`), the counter increments by 1 (`count <= count + 1`). You can instantiate this module in your top-level design hierarchy and connect it to other modules or input/output signals as needed.