Sure, here's an example of a 3x8 decoder with active-low outputs implemented using SystemVerilog:
module decoder_3x8_active_low(
input logic [2:0] in,
output logic [7:0] out
);
assign out =
{in[2]&in[1]&in[0], in[2]&in[1]&
in[0], in[2]&
in[1]&in[0], in[2]&
in[1]&
in[0],
in[2]&in[1]&in[0],
in[2]&in[1]&
in[0],
in[2]&
in[1]&in[0],
in[2]&
in[1]&
in[0]}; endmodule
In this code, we define a module called `decoder_3x8_active_low` with one input port `in`, which is a 3-bit binary value representing the input to the decoder, and eight output ports `out`, which are active-low signals representing the decoded output.
The `assign` statement uses the logical operators `&` and `
` to implement the decoding functionality. Each bit of the output `out` is set to 0 except for the bit corresponding to the input signal `in`, which is set to 1. Since the outputs are active-low, we use the bitwise NOT operator `
` to invert the output values.
For example, if the input signal `in` is `3’b010`, the output signal `out` will be set to `8’b11110111`, which represents the active-low output value of the second bit position.
You can instantiate this module in your top-level design hierarchy and connect it to other modules or input/output signals as needed. Note that you can modify the code to implement a decoder with a different number of inputs by changing the bit width of the input signal and the number of output signals, and modifying the decoding logic accordingly.