Sure, here’s an example of a 3-bit synchronous up counter with enable implemented using SystemVerilog:
module up_counter_3bit_enable(
input logic clk,
input logic enable,
output logic [2:0] count
);
always_ff @(posedge clk) begin
if (enable) begin
count <= count + 1;
end
end
endmodule
In this code, we define a module called `up_counter_3bit_enable` with three ports: `clk`, `enable`, and `count`. The `clk` input is used as the clock signal, the `enable` input is an enable signal which allows the counter to count when it is asserted, and the `count` output is a 3-bit binary counter that counts from 0 to 7.
The `always_ff` block is used to describe the behavior of the counter. The `posedge clk` event triggers the counter to increment on every rising edge of the clock signal. The `enable` signal is used to enable or disable the counter from counting.
When the enable signal is asserted (`enable = 1`), the counter increments by 1 (`count <= count + 1`). When the enable signal is deasserted (`enable = 0`), the counter stops counting and maintains its current value. You can instantiate this module in your top-level design hierarchy and connect it to other modules or input/output signals as needed. Note that you can modify the code to implement a down counter or an up/down counter by changing the logic in the always_ff block to decrement or toggle the counter value.