Verilog code to implement a 4-to-1 multiplexer circuit.

Here’s an example Verilog code to implement a 4-to-1 multiplexer circuit:

module mux4to1 (output reg out, input [3:0] in, input [1:0] select);

    always @(*) begin
        case (select)
            2'b00: out = in[0];
            2'b01: out = in[1];
            2'b10: out = in[2];
            2'b11: out = in[3];
        endcase
    end

endmodule

This code defines a module called “mux4to1” that implements a 4-to-1 multiplexer. The output “out” is a registered output, which means that it is updated only on clock edges. The input “in” is a 4-bit vector that contains the four data inputs to the multiplexer, and “select” is a 2-bit vector that determines which input is passed to the output.

The “always @(*)” block is a combinational logic block that updates the “out” output based on the inputs and select signal. The case statement checks the value of the “select” signal and assigns the appropriate input to the output. For example, if “select” is 2’b00, then the first input “in[0]” is passed to the output. Likewise, if “select” is 2’b01, then the second input “in[1]” is passed to the output, and so on.

Note that this Verilog code assumes that the “out” output and the “in” inputs are all 1-bit signals, and the “select” input is a 2-bit signal. If you want to use multi-bit signals, you would need to modify the code accordingly.