Verilog code to implement a 4-bit up/down counter circuit.

Here’s an example Verilog code to implement a 4-bit up/down counter circuit:

module up_down_counter (output reg [3:0] out, input clk, input up, input down, input reset);

    always @(posedge clk, negedge reset) begin
        if (!reset) begin
            out <= 4'b0000;
        end
        else if (up) begin
            out <= out + 1;
        end 
        else if (down) begin
            out <= out - 1;
        end
    end

endmodule

This code defines a module called "up_down_counter" that implements a 4-bit up/down counter. The output "out" is a registered output, which means that it is updated only on clock edges. The input "clk" is the clock input, and "up" and "down" are control signals that determine whether the counter should count up or down. The "reset" signal resets the counter to 0.

The "always @(posedge clk, negedge reset)" block is a sequential logic block that updates the "out" output based on the clock and reset signals. If the "reset" signal is low, then the counter is reset to 0. Otherwise, if the "up" signal is high, then the counter increments by 1 on the positive edge of the clock. If the "down" signal is high, then the counter decrements by 1 on the positive edge of the clock.

Note that this Verilog code assumes that the "out" output, the "up" and "down" control signals, and the "reset" signal are all 1-bit signals. If you want to use multi-bit signals, you would need to modify the code accordingly. Additionally, this code implements a synchronous counter. If you wanted to implement an asynchronous counter, you would need to modify the code accordingly.