Here’s an example Verilog code to implement a 4-bit counter with asynchronous reset:
module counter (output reg [3:0] count, input clk, reset);
always @(posedge clk, negedge reset) begin
if (!reset) begin
count <= 4'b0000;
end
else begin
count <= count + 1;
end
end
endmodule
This code defines a module called "counter" that implements a 4-bit counter with an asynchronous reset. The output "count" is a registered output, which means that it is updated only on clock edges. The input "clk" is the clock input, and "reset" is the asynchronous reset input.
The "always @(posedge clk, negedge reset)" block is a sequential logic block that updates the "count" output based on the clock and reset signals. If the "reset" signal is low, then the counter is reset to 0. Otherwise, on every positive edge of the clock, the counter increments by 1.
Note that this Verilog code assumes that the "count" output, the "clk" input, and the "reset" input are all 1-bit signals. If you want to use multi-bit signals, you would need to modify the code accordingly. Additionally, this code implements a rising-edge triggered counter. If you wanted to implement a falling-edge triggered counter, you would need to modify the code accordingly.