Implement a 8-input priority encoder using SystemVerilog.

Sure, here’s an example of an 8-input priority encoder implemented using SystemVerilog:

module priority_encoder_8bit(
  input logic [7:0] in,
  output logic [2:0] out
);

  assign out = (in[7]) ? 3'b111 :
               (in[6]) ? 3'b110 :
               (in[5]) ? 3'b101 :
               (in[4]) ? 3'b100 :
               (in[3]) ? 3'b011 :
               (in[2]) ? 3'b010 :
               (in[1]) ? 3'b001 :
                         3'b000 ;

endmodule

In this code, we define a module called `priority_encoder_8bit` with one input port `in`, which is an 8-bit binary value representing the priority encoder inputs, and an output port `out`, which is a 3-bit binary value representing the highest priority input.

The `assign` statement assigns the output signal `out` the value of the highest priority input signal based on its position in the input binary value `in`. The priority encoder works by encoding the highest priority input signal with a binary value that represents its position in the input signal.

For example, if the input signal `in` is `8’b00110010`, the output signal `out` will be set to `3’b110`, which represents the position of the highest priority input signal (the fourth input signal).

If multiple input signals are asserted, the priority encoder encodes the input signal with the highest priority (the input signal with the highest position in the binary value `in`).

You can instantiate this module in your top-level design hierarchy and connect it to other modules or input/output signals as needed. Note that you can modify the code to implement a priority encoder with a different number of inputs by changing the bit width of the input signal and the output binary value, and modifying the priority encoding logic accordingly.