Implement a 4-to-1 multiplexer using SystemVerilog.

Sure, here’s an example of a 4-to-1 multiplexer implemented using SystemVerilog:

module mux_4to1(
  input logic [3:0] in,
  input logic [1:0] sel,
  output logic out
);

  assign out = (sel == 2'b00) ? in[0] :
               (sel == 2'b01) ? in[1] :
               (sel == 2'b10) ? in[2] :
                                in[3];

endmodule

In this code, we define a module called `mux_4to1` with three ports: `in`, `sel`, and `out`. The `in` input is a 4-bit binary input that represents the four possible input signals, the `sel` input is a 2-bit binary input that represents the selection signal, and the `out` output is a single-bit binary output that represents the selected signal.

The `assign` statement assigns the output signal `out` the value of the selected input signal based on the value of the selection signal `sel`. The ternary operator is used to select the appropriate input signal based on the value of `sel`.

For example, if the `sel` signal is `2’b10`, the output signal `out` will be the value of the third input signal (`in[2]`).

You can instantiate this module in your top-level design hierarchy and connect it to other modules or input/output signals as needed. Note that you can modify the code to implement a wider or narrower multiplexer by changing the bit width of the input and output signals, and the number of selection bits.