Sure, here’s an example of a 4-bit parallel-out, serial-in (POSI) shift register implemented using SystemVerilog:
module posi_shift_register_4bit(
input logic parallel_in,
input logic clock,
input logic reset,
input logic enable,
output logic [3:0] serial_out
);
logic [3:0] shift_reg;
always_ff @(posedge clock) begin
if (reset) begin
shift_reg <= 4'b0000;
end else if (enable) begin
shift_reg <= {shift_reg[2:0], parallel_in};
end
end
assign serial_out = shift_reg;
endmodule
In this code, we define a module called `posi_shift_register_4bit` with four input ports `parallel_in`, `clock`, `reset`, and `enable`, and one output port `serial_out`. The `parallel_in` input is a single-bit binary value to be loaded into the shift register, the `clock` input is a single-bit binary value representing the clock signal, the `reset` input is a single-bit binary value representing the reset signal, the `enable` input is a single-bit binary value representing the enable signal, and the `serial_out` output is a 4-bit binary value representing the output of the shift register.
The `shift_reg` signal is a 4-bit binary value representing the contents of the shift register.
Inside the `always_ff` block, we use an if statement to describe the behavior of the shift register. If `reset` is asserted, the shift register is reset to 0. If `enable` is asserted, the shift register is updated by shifting the contents of the register one bit to the left and loading the `parallel_in` value into the most significant bit position.
The `assign` statement is used to assign the value of the `shift_reg` signal to the `serial_out` output, which represents the output of the shift register.
You can instantiate this module in your top-level design hierarchy and connect it to other modules or input/output signals as needed. Note that you can modify the code to implement a shift register with a different number of bits by changing the bit width of the input and output signals, and modifying the shift register logic accordingly.