Sure, here’s an example of a 3-to-8 decoder implemented using SystemVerilog:
module decoder_3to8( input logic [2:0] in, output logic [7:0] out ); assign out = 8'b00000001 << in; endmodule
In this code, we define a module called `decoder_3to8` with two ports: `in` and `out`. The `in` input is a 3-bit binary input that represents the input selection, and the `out` output is an 8-bit binary output that represents the selected output.
The `assign` statement assigns the output signal `out` the value of a bit-shifted binary number. The `<<` operator performs a left bit-shift operation by the number of bits specified by the input signal `in`. This results in a binary number with a single '1' bit at the corresponding position of the input selection, and all other bits set to '0'. For example, if the `in` signal is `3'b010`, the output signal `out` will be `8'b00000100`. This represents the selected output of the third output line (counting from 0) of the 8 possible output lines of the 3-to-8 decoder. You can instantiate this module in your top-level design hierarchy and connect it to other modules or input/output signals as needed.