Sure, here’s an example of a 3-input AND gate implemented using SystemVerilog:
module and_gate_3input( input logic a, input logic b, input logic c, output logic out ); assign out = a & b & c; endmodule
In this code, we define a module called `and_gate_3input` with three input ports `a`, `b`, and `c`, and an output port `out`. The `a`, `b`, and `c` inputs are single-bit binary values, and the `out` output is a single-bit binary value that represents the result of the AND operation.
The `assign` statement assigns the output signal `out` the result of the AND operation between the three input signals `a`, `b`, and `c`.
For example, if the `a`, `b`, and `c` signals are all set to 1, the output signal `out` will be set to 1.
You can instantiate this module in your top-level design hierarchy and connect it to other modules or input/output signals as needed. Note that you can modify the code to implement an AND gate with a different number of inputs by changing the number of input ports and modifying the AND operation accordingly.