Sure, here’s an example of a 3-bit shift register with parallel load implemented using SystemVerilog:
module shift_register_3bit(
input logic clk,
input logic [2:0] in,
input logic load,
output logic [2:0] out
);
always_ff @(posedge clk) begin
if (load) begin
out <= in;
end
else begin
out <= {out[1:0], 1'b0};
end
end
endmodule
In this code, we define a module called `shift_register_3bit` with four ports: `clk`, `in`, `load`, and `out`. The `clk` input is used as the clock signal, the `in` input is a 3-bit binary input that represents the data to be loaded in parallel, the `load` input is a control signal which loads the input data when it is asserted, and the `out` output is a 3-bit binary shift register that shifts the data to the left on every clock cycle.
The `always_ff` block is used to describe the behavior of the shift register. The `posedge clk` event triggers the shift register to shift the data on every rising edge of the clock signal.
When the `load` signal is asserted (`load = 1`), the shift register loads the input data (`out <= in`). When the `load` signal is deasserted (`load = 0`), the shift register shifts the data to the left (`out <= {out[1:0], 1'b0}`). This is achieved by concatenating the two least significant bits of the output signal (`out[1:0]`) with a '0' bit at the most significant position (`1'b0`). You can instantiate this module in your top-level design hierarchy and connect it to other modules or input/output signals as needed. Note that you can modify the code to implement a right shift register or a bidirectional shift register by changing the logic in the always_ff block to shift the data to the right or to alternate the shift direction based on a control signal.