Implement a 2-input AND gate using SystemVerilog.

Sure, here’s an example of a 2-input AND gate implemented using SystemVerilog:

module and_gate(
  input logic a,
  input logic b,
  output logic out
);

  assign out = a & b;

endmodule

In this code, we define a module called `and_gate` with two input ports `a` and `b`, and an output port `out`. The `logic` data type is used to specify that the input and output signals are digital logic signals.

The `assign` statement assigns the output signal `out` the value of the logical AND operation between `a` and `b`. The `&` operator performs a bitwise AND operation on the two input signals.

You can instantiate this module in your top-level design hierarchy and connect it to other modules or input/output signals as needed.