In SystemVerilog, a module is a hardware component that can be instantiated and connected to other modules or components to form a larger system. Here is an example of a module definition:
module my_module(input a, output b);
// module implementation
endmodule
To instantiate a module in SystemVerilog, you use the module name followed by the instance name and a list of port connections, enclosed in parentheses. Here is an example of a module instantiation:
my_module inst1 (.a(a_signal), .b(b_signal));
In this example, a module named “my_module” is instantiated with the instance name “inst1”. The input signal “a_signal” is connected to the input port “a” of the module, and the output signal “b_signal” is connected to the output port “b” of the module.
There are two types of module instances in SystemVerilog: named and anonymous. Named instances are instances that have a specific instance name, while anonymous instances are instances that do not have a name. Here is an example of a named instance:
my_module inst1 (.a(a_signal), .b(b_signal));
In this example, “inst1” is the name of the instance.
Here is an example of an anonymous instance:
new my_module (.a(a_signal), .b(b_signal));
In this example, “new” is the keyword used to indicate that an anonymous instance is being created.
Anonymous instances are typically used when multiple instances of the same module are needed, but the instances do not need to be uniquely named. Named instances are used when the instance needs to be referred to elsewhere in the code or when the instance name needs to be specified for debugging or reporting purposes.
Overall, module instantiation is an important concept in SystemVerilog, as it allows designers to create complex hardware systems by instantiating and connecting modules together.