In SystemVerilog, arrays can be either packed or unpacked, depending on how they are stored in memory.
Unpacked arrays are arrays in which each element is a separate variable that is stored in memory. For example, an unpacked array of 4 8-bit elements would be stored in memory as 4 separate 8-bit variables. Unpacked arrays are declared using square brackets “[]” after the variable name and before the data type.
Packed arrays, on the other hand, are arrays in which multiple elements are stored in a single variable. For example, a packed array of 4 8-bit elements would be stored in memory as a single 32-bit variable. Packed arrays are declared using square brackets “[]” after the data type and before the variable name, with an additional keyword “packed” before the data type.
The main difference between packed and unpacked arrays is how they are stored in memory. Packed arrays save memory space by packing multiple elements into a single variable, but they require additional syntax to access individual elements. Unpacked arrays, on the other hand, are easier to use and access individual elements, but they require more memory space.
In general, packed arrays are often used for bit-level operations and for defining signals that have a fixed structure, such as buses and registers. Unpacked arrays are often used for data structures that have a variable size, such as arrays and queues.
It’s also worth noting that SystemVerilog supports both signed and unsigned packed and unpacked arrays, as well as multi-dimensional arrays.