Explain the concept of constrained randomization and its role in SystemVerilog verification.

Constrained randomization is a methodology used in SystemVerilog verification to generate randomized test stimuli that are both realistic and comprehensive. Constrained randomization is based on the idea of generating random input values that are constrained by specific rules or constraints, ensuring that the generated stimuli are realistic and meaningful.

Constrained randomization is typically used in conjunction with the object-oriented programming (OOP) features of SystemVerilog, such as classes and inheritance. By using classes and inheritance, designers can define the properties and constraints of the input stimuli in a modular and hierarchical way, making it easier to generate complex and realistic stimuli.

Here is an example of using constrained randomization to generate test stimuli:

class my_test;
    rand int a;
    randc logic [7:0] b;
    constraint a_c { a inside { 0:100 }; }
    constraint b_c { b != 8'hFF; }
endclass

module my_module;
    my_test test;
    initial begin
        repeat(10) begin
            if (test.randomize() with { b == 8'h01; }) begin
                $display("a = %d, b = %h", test.a, test.b);
            end
        end
    end
endmodule

In this example, a class “my_test” is defined with two randomized variables, “a” and “b”, and two constraints, “a_c” and “b_c”. The “a_c” constraint ensures that the value of “a” is between 0 and 100, while the “b_c” constraint ensures that the value of “b” is not equal to 8’hFF.

In the “my_module” module, an instance of the “my_test” class is created, and the “randomize()” method is called to generate randomized test stimuli. The “with { b == 8’h01; }” constraint is used to further constrain the value of “b” to be equal to 8’h01. The $display statement is used to print the values of “a” and “b” for each generated test stimulus.

Overall, constrained randomization is a powerful methodology used in SystemVerilog verification to generate randomized test stimuli that are both realistic and comprehensive. By using constrained randomization, designers can generate test stimuli that cover a wide range of scenarios and edge cases, helping to ensure the correct functionality of the hardware design.