In SystemVerilog, there are two types of assignments that can be used in procedural blocks: blocking and non-blocking assignments. The main difference between them is how they are executed and how they affect the simulation.
Blocking assignments are executed in a sequential order, meaning that each assignment must complete before the next one can begin. The value assigned to a signal using a blocking assignment is immediately updated, and any subsequent statements wait until the assignment is complete. Blocking assignments are denoted using the “=” operator.
Example of a blocking assignment:
a = b + c; d = a - e;
In this example, the value of “a” is first updated before the second statement is executed.
Non-blocking assignments, on the other hand, are executed in parallel, meaning that all assignments are scheduled to take place simultaneously. The value assigned to a signal using a non-blocking assignment is not updated until all other non-blocking assignments have been executed. Non-blocking assignments are denoted using the “<=" operator. Example of a non-blocking assignment:
a <= b + c; d <= a - e;
In this example, the value of "a" is scheduled to be updated, but the value is not actually updated until all other non-blocking assignments have been executed. This allows multiple signals to be updated simultaneously, without affecting the order of execution.
The main advantage of using non-blocking assignments is that they allow for more accurate modeling of sequential logic, particularly in simulations where timing is important. By using non-blocking assignments, you can model the behavior of a sequential circuit more accurately and ensure that the simulation behaves as expected. However, it's important to use them correctly, as using non-blocking assignments in a combinatorial circuit can lead to unexpected behavior and simulation errors.