Here’s an example Verilog code to implement a 4-bit Johnson counter circuit: module johnson_counter (output reg [3:0] count, input clk); always @(posedge clk) begin count <= {count[2], count[3], count[2], count[3]}; end endmodule This code defines a module called “johnson_counter” that implements a 4-bit Johnson counter. The output “count” is a registered output that represents the … Read more
Here’s an example Verilog code to implement a 4-bit ring counter circuit: module ring_counter (output reg [3:0] count, input clk); always @(posedge clk) begin count <= {count[2:0], count[3]}; end endmodule This code defines a module called “ring_counter” that implements a 4-bit ring counter. The output “count” is a registered output that represents the current state … Read more
Here’s an example Verilog code to implement a 4-bit shift register circuit with a parallel in/serial out: module shift_register_parallel (output serial_out, input [3:0] parallel_in, input shift); reg [3:0] shift_reg; always @(posedge shift) begin shift_reg <= parallel_in; end assign serial_out = shift_reg[0]; always @(posedge shift) begin shift_reg <= {shift_reg[2:0], 1’b0}; end endmodule This code defines a … Read more
Here’s an example Verilog code to implement a 4-bit shift register circuit with a serial in/parallel out: module shift_register (output reg [3:0] parallel_out, input serial_in, input shift); reg [3:0] shift_reg; always @(posedge shift) begin if (shift) begin shift_reg <= {shift_reg[2:0], serial_in}; end end assign parallel_out = shift_reg; endmodule This code defines a module called “shift_register” … Read more
Here’s an example Verilog code to implement a 4-bit counter with load enable: module counter_load (output reg [3:0] count, input clk, input load, input [3:0] data); always @(posedge clk) begin if (load) begin count <= data; end else begin count <= count + 4’b0001; end end endmodule This code defines a module called “counter_load” that … Read more
Here’s an example Verilog code to implement a 4-bit counter with asynchronous reset: module counter (output reg [3:0] count, input clk, reset); always @(posedge clk, negedge reset) begin if (!reset) begin count <= 4’b0000; end else begin count <= count + 1; end end endmodule This code defines a module called “counter” that implements a … Read more
Here’s an example Verilog code to implement a 4-bit half adder circuit: module half_adder (output sum, carry, input a, b); assign sum = a ^ b; assign carry = a & b; endmodule This code defines a module called “half_adder” that implements a 4-bit half adder. The output “sum” represents the sum of the two … Read more
Here’s an example Verilog code to implement a 4-bit subtractor circuit: module subtractor (output reg [3:0] difference, input [3:0] minuend, subtrahend, input borrow_in); always @(minuend, subtrahend, borrow_in) begin reg borrow; difference[0] = minuend[0] ^ subtrahend[0] ^ borrow_in; borrow = ( minuend[0] & subtrahend[0]) | (( minuend[0] | subtrahend[0]) & borrow_in); difference[1] = minuend[1] ^ subtrahend[1] … Read more
Here’s an example Verilog code to implement a 4-bit ripple carry adder circuit: module ripple_carry_adder (output reg [3:0] sum, output reg carry_out, input [3:0] a, b, input carry_in); always @(a, b, carry_in) begin reg carry; sum[0] = a[0] ^ b[0] ^ carry_in; carry = (a[0] & b[0]) | (a[0] & carry_in) | (b[0] & carry_in); … Read more
Here’s an example Verilog code to implement a T flip-flop circuit: module t_ff (output reg q, input t, clk, reset); always @(posedge clk, negedge reset) begin if (!reset) begin q <= 1’b0; end else begin if (t) begin q <= q; end end end endmodule This code defines a module called “t_ff” that implements a … Read more