Here’s an example Verilog code to implement a 4-bit adder-subtractor circuit: module add_sub (output reg [3:0] result, input [3:0] a, input [3:0] b, input sub); always @(a, b, sub) begin if (sub) result = a – b; else result = a + b; end endmodule This code defines a module called “add_sub” that implements a … Read more
Here’s an example Verilog code to implement a 4-bit demultiplexer circuit with enable: module demux_with_enable (output reg [3:0] out0, output reg [3:0] out1, input [3:0] in, input enable, input select); always @(*) begin if (enable) begin if (select) out1 = in; else out0 = in; end end endmodule This code defines a module called “demux_with_enable” … Read more
Here’s an example Verilog code to implement a 4-bit multiplexer circuit with enable: module mux_with_enable (output reg [3:0] out, input [3:0] in0, input [3:0] in1, input enable); always @(*) begin if (enable) out = in1; else out = in0; end endmodule This code defines a module called “mux_with_enable” that implements a 4-bit multiplexer with enable. … Read more
Here’s an example Verilog code to implement a 4-bit decoder circuit: module decoder (output reg [15:0] decoded, input [3:0] select); always @(*) begin case (select) 4’b0001: decoded = 16’b0000000000000001; 4’b0010: decoded = 16’b0000000000000010; 4’b0100: decoded = 16’b0000000000000100; 4’b1000: decoded = 16’b0000000000001000; default: decoded = 16’b0000000000000000; endcase end endmodule This code defines a module called “decoder” … Read more
Here’s an example Verilog code to implement a 4-bit encoder circuit: module encoder (output reg [3:0] encoded, input [1:0] select); always @(*) begin case (select) 2’b00: encoded = 4’b0001; 2’b01: encoded = 4’b0010; 2’b10: encoded = 4’b0100; 2’b11: encoded = 4’b1000; endcase end endmodule This code defines a module called “encoder” that implements a 4-bit … Read more
Here’s an example Verilog code to implement a 4-bit priority encoder circuit: module priority_encoder (output reg [1:0] encoded, input [3:0] data); always @(*) begin casez (data) 4’b0000: encoded = 2’b00; 4’b0001: encoded = 2’b01; 4’b0010: encoded = 2’b10; default: encoded = 2’b11; endcase end endmodule This code defines a module called “priority_encoder” that implements a … Read more
Here’s an example Verilog code to implement a 4-bit barrel shifter circuit: module barrel_shifter (output reg [3:0] shifted, input [3:0] data, input [1:0] shift_amt, input shift_dir); always @(*) begin case ({shift_dir, shift_amt}) 2’b00: shifted = data; // no shift 2’b01: shifted = {data[2:0], 1’b0}; // shift left 2’b10: shifted = {1’b0, data[3:1]}; // shift right … Read more
Here’s an example Verilog code to implement a 4-bit gray code to binary converter circuit: module gray_to_binary (output reg [3:0] binary, input [3:0] gray); assign binary[0] = gray[0]; assign binary[1] = gray[1] ^ binary[0]; assign binary[2] = gray[2] ^ binary[1]; assign binary[3] = gray[3] ^ binary[2]; endmodule This code defines a module called “gray_to_binary” that … Read more
Here’s an example Verilog code to implement a 4-bit binary to gray code converter circuit: module binary_to_gray (output reg [3:0] gray, input [3:0] binary); assign gray[0] = binary[0]; assign gray[1] = binary[1] ^ binary[0]; assign gray[2] = binary[2] ^ binary[1]; assign gray[3] = binary[3] ^ binary[2]; endmodule This code defines a module called “binary_to_gray” that … Read more
Here’s an example Verilog code to implement a 4-bit gray code counter circuit: module gray_counter (output reg [3:0] count, input clk); always @(posedge clk) begin count <= count ^ (count >> 1); end endmodule This code defines a module called “gray_counter” that implements a 4-bit gray code counter. The output “count” is a registered output … Read more