Sure, here’s an example of a 2-bit comparator implemented using SystemVerilog: module comparator_2bit( input logic [1:0] a, input logic [1:0] b, output logic eq, output logic gt, output logic lt ); assign eq = (a == b); assign gt = (a > b); assign lt = (a < b); endmodule In this code, we define ... Read more
Sure, here’s an example of a 4-bit ripple carry adder with carry-in and carry-out implemented using SystemVerilog: module ripple_carry_adder_4bit( input logic [3:0] a, input logic [3:0] b, input logic cin, output logic [3:0] sum, output logic cout ); logic [3:0] carry; assign carry[0] = cin; generate for (genvar i = 1; i < 4; i++) ... Read more
Sure, here’s an example of an 8-input priority encoder implemented using SystemVerilog: module priority_encoder_8bit( input logic [7:0] in, output logic [2:0] out ); assign out = (in[7]) ? 3’b111 : (in[6]) ? 3’b110 : (in[5]) ? 3’b101 : (in[4]) ? 3’b100 : (in[3]) ? 3’b011 : (in[2]) ? 3’b010 : (in[1]) ? 3’b001 : 3’b000 … Read more
Sure, here’s an example of a 4-bit shift register with left and right shift options implemented using SystemVerilog: module shift_register_4bit( input logic clk, input logic [3:0] in, input logic left_shift, input logic right_shift, output logic [3:0] out ); always_ff @(posedge clk) begin if (left_shift) begin out
Sure, here’s an example of a 3-input AND gate implemented using SystemVerilog: module and_gate_3input( input logic a, input logic b, input logic c, output logic out ); assign out = a & b & c; endmodule In this code, we define a module called `and_gate_3input` with three input ports `a`, `b`, and `c`, and an … Read more
Sure, here’s an example of a 3-bit synchronous down counter with enable implemented using SystemVerilog: module down_counter_3bit_enable( input logic clk, input logic enable, output logic [2:0] count ); always_ff @(posedge clk) begin if (enable) begin count
Sure, here’s an example of a 4-to-1 multiplexer implemented using SystemVerilog: module mux_4to1( input logic [3:0] in, input logic [1:0] sel, output logic out ); assign out = (sel == 2’b00) ? in[0] : (sel == 2’b01) ? in[1] : (sel == 2’b10) ? in[2] : in[3]; endmodule In this code, we define a module … Read more
Sure, here’s an example of a 4-bit ALU implemented using SystemVerilog: module alu_4bit( input logic [3:0] a, input logic [3:0] b, input logic [2:0] op, output logic [3:0] out ); always_comb begin case(op) 3’b000: out = a + b; // add 3’b001: out = a – b; // subtract 3’b010: out = a & b; … Read more
Sure, here’s an example of a 3-bit shift register with parallel load implemented using SystemVerilog: module shift_register_3bit( input logic clk, input logic [2:0] in, input logic load, output logic [2:0] out ); always_ff @(posedge clk) begin if (load) begin out
Sure, here’s an example of a 4×16 decoder with active-low outputs implemented using SystemVerilog: module decoder_4x16_active_low( input logic [3:0] in, output logic [15:0] out ); assign out = (16’b0000000000000001