Sure, here’s an example of a 4-bit magnitude comparator implemented using only NOR gates in SystemVerilog: module magnitude_comparator_4bit_nor( input logic [3:0] a, input logic [3:0] b, output logic eq, output logic gt, output logic lt ); logic [3:0] na, nb, diff; assign na = a; assign nb = b; assign diff = na + b; … Read more
Sure, here’s an example of a 2:4 demultiplexer implemented using gates in SystemVerilog: module demux_2to4_gates( input logic in, input logic [1:0] sel, output logic out0, output logic out1, output logic out2, output logic out3 ); assign out0 = in & sel[1] & sel[0]; assign out1 = in & sel[1] & sel[0]; assign out2 = in … Read more
Sure, here’s an example of a 4-bit parallel-out, serial-in (POSI) shift register implemented using SystemVerilog: module posi_shift_register_4bit( input logic parallel_in, input logic clock, input logic reset, input logic enable, output logic [3:0] serial_out ); logic [3:0] shift_reg; always_ff @(posedge clock) begin if (reset) begin shift_reg <= 4’b0000; end else if (enable) begin shift_reg <= {shift_reg[2:0], … Read more
Sure, here’s an example of a 4-bit binary to BCD (Binary Coded Decimal) converter implemented using SystemVerilog: module binary_to_bcd_converter_4bit( input logic [3:0] bin, output logic [7:0] bcd ); always_comb begin case (bin) 4’b0000: bcd = 8’b00000001; 4’b0001: bcd = 8’b00000010; 4’b0010: bcd = 8’b00000100; 4’b0011: bcd = 8’b00000110; 4’b0100: bcd = 8’b00001000; 4’b0101: bcd = … Read more
Sure, here’s an example of a 4-bit carry-lookahead adder implemented using SystemVerilog: module carry_lookahead_adder_4bit( input logic [3:0] a, input logic [3:0] b, input logic cin, output logic [3:0] sum, output logic cout ); logic [3:0] p, g, c; assign p = a ^ b; assign g = a & b; assign c[0] = cin; assign … Read more
Sure, here’s an example of a 3×8 decoder with active-low outputs implemented using SystemVerilog: module decoder_3x8_active_low( input logic [2:0] in, output logic [7:0] out ); assign out = {in[2]&in[1]&in[0], in[2]&in[1]& in[0], in[2]& in[1]&in[0], in[2]& in[1]& in[0], in[2]&in[1]&in[0], in[2]&in[1]& in[0], in[2]& in[1]&in[0], in[2]& in[1]& in[0]}; endmodule In this code, we define a module called `decoder_3x8_active_low` with … Read more
Sure, here’s an example of a 4-bit parallel-in, serial-out (PISO) shift register implemented using SystemVerilog: module piso_shift_register_4bit( input logic [3:0] parallel_in, input logic clock, input logic reset, output logic serial_out ); logic [3:0] shift_reg; always_ff @(posedge clock) begin if (reset) begin shift_reg <= 4’b0000; end else begin shift_reg <= {parallel_in, shift_reg[3:1]}; end end assign serial_out … Read more
Sure, here’s an example of a 2:1 multiplexer implemented using gates in SystemVerilog: module mux_2to1_using_gates( input logic a, input logic b, input logic sel, output logic out ); assign out = ( sel & a) | (sel & b); endmodule In this code, we define a module called `mux_2to1_using_gates` with three input ports `a`, `b`, … Read more
Sure, here’s an example of a 4-bit barrel shifter implemented using SystemVerilog: module barrel_shifter_4bit( input logic [3:0] in, input logic [1:0] shift_amount, input logic shift_direction, output logic [3:0] out ); always_comb begin case (shift_direction) 1’b0: out = {in[3-shift_amount[1]:0], in[3:4-shift_amount]}; 1’b1: out = {in[shift_amount], in[3:shift_amount]}; default: out = in; endcase end endmodule In this code, we … Read more
Sure, here’s an example of a 4×2 priority encoder implemented using SystemVerilog: module priority_encoder_4x2( input logic [3:0] in, output logic [1:0] out, output logic valid ); always_comb begin casez(in) 4’b0001: begin out = 2’b00; valid = 1; end 4’b001x: begin out = 2’b01; valid = 1; end 4’b01xx: begin out = 2’b10; valid = 1; … Read more