Sandip

Sure, here’s an example of a 4-to-1 multiplexer implemented using SystemVerilog: module mux_4to1( input logic [3:0] in, input logic [1:0] sel, output logic out ); assign out = (sel == 2’b00) ? in[0] : (sel == 2’b01) ? in[1] : (sel == 2’b10) ? in[2] : in[3]; endmodule In this code, we define a module … Read more

Sure, here’s an example of a 4-bit ALU implemented using SystemVerilog: module alu_4bit( input logic [3:0] a, input logic [3:0] b, input logic [2:0] op, output logic [3:0] out ); always_comb begin case(op) 3’b000: out = a + b; // add 3’b001: out = a – b; // subtract 3’b010: out = a & b; … Read more

Sure, here’s an example of a 3-bit shift register with parallel load implemented using SystemVerilog: module shift_register_3bit( input logic clk, input logic [2:0] in, input logic load, output logic [2:0] out ); always_ff @(posedge clk) begin if (load) begin out

Sure, here’s an example of a 4×16 decoder with active-low outputs implemented using SystemVerilog: module decoder_4x16_active_low( input logic [3:0] in, output logic [15:0] out ); assign out = (16’b0000000000000001

Sure, here’s an example of a priority encoder with 8 inputs implemented using SystemVerilog: module priority_encoder_8to3( input logic [7:0] in, output logic [2:0] out ); always_comb begin casez(in) 8’b00000001: out = 3’b000; 8’b00000010: out = 3’b001; 8’b00000100: out = 3’b010; 8’b00001000: out = 3’b011; 8’b00010000: out = 3’b100; 8’b00100000: out = 3’b101; 8’b01000000: out = … Read more

Sure, here’s an example of a 3-bit synchronous up counter with enable implemented using SystemVerilog: module up_counter_3bit_enable( input logic clk, input logic enable, output logic [2:0] count ); always_ff @(posedge clk) begin if (enable) begin count

Sure, here’s an example of a 2-input XOR gate implemented using SystemVerilog: module xor_gate( input logic a, input logic b, output logic out ); assign out = a ^ b; endmodule In this code, we define a module called `xor_gate` with two input ports `a` and `b`, and an output port `out`. The `logic` data … Read more

Sure, here’s an example of a 3-to-8 decoder implemented using SystemVerilog: module decoder_3to8( input logic [2:0] in, output logic [7:0] out ); assign out = 8’b00000001

Sure, here’s an example of a 4-bit binary counter with asynchronous reset implemented using SystemVerilog: module counter_4bit_async_reset( input logic clk, input logic reset, output logic [3:0] count ); always_ff @(posedge clk, negedge reset) begin if (!reset) begin count

Sure, here’s an example of a 2-input AND gate implemented using SystemVerilog: module and_gate( input logic a, input logic b, output logic out ); assign out = a & b; endmodule In this code, we define a module called `and_gate` with two input ports `a` and `b`, and an output port `out`. The `logic` data … Read more