Write a SystemVerilog code for a 4-bit binary to BCD (Binary Coded Decimal) converter.

Sure, here’s an example of a 4-bit binary to BCD (Binary Coded Decimal) converter implemented using SystemVerilog:

module binary_to_bcd_converter_4bit(
  input logic [3:0] bin,
  output logic [7:0] bcd
);

  always_comb begin
    case (bin)
      4'b0000: bcd = 8'b00000001;
      4'b0001: bcd = 8'b00000010;
      4'b0010: bcd = 8'b00000100;
      4'b0011: bcd = 8'b00000110;
      4'b0100: bcd = 8'b00001000;
      4'b0101: bcd = 8'b00001001;
      4'b0110: bcd = 8'b00001100;
      4'b0111: bcd = 8'b00001110;
      4'b1000: bcd = 8'b00010000;
      4'b1001: bcd = 8'b00010001;
      4'b1010: bcd = 8'b00010100;
      4'b1011: bcd = 8'b00010110;
      4'b1100: bcd = 8'b00011000;
      4'b1101: bcd = 8'b00011001;
      4'b1110: bcd = 8'b00011100;
      4'b1111: bcd = 8'b00011110;
      default: bcd = 8'b00000000;
    endcase
  end

endmodule

In this code, we define a module called `binary_to_bcd_converter_4bit` with one input port `bin`, which is a 4-bit binary value representing the binary input, and one output port `bcd`, which is an 8-bit binary value representing the BCD output.

The `case` statement uses the binary input value `bin` to select the appropriate BCD output value. Each case corresponds to a specific binary input value, and the output value is set accordingly. If the binary input value is not one of the cases listed, the BCD output is set to 0.

For example, if the input signal `bin` is `4’b1010`, the output signal `bcd` will be set to `8’b00010100`, which represents the BCD value of 10.

You can instantiate this module in your top-level design hierarchy and connect it to other modules or input/output signals as needed. Note that you can modify the code to implement a BCD converter with a different number of bits by changing the bit width of the input and output signals, and modifying the BCD conversion logic accordingly.