Here’s an example Verilog code to implement a 4-bit counter with load enable:
module counter_load (output reg [3:0] count, input clk, input load, input [3:0] data);
always @(posedge clk) begin
if (load) begin
count <= data;
end
else begin
count <= count + 4'b0001;
end
end
endmodule
This code defines a module called "counter_load" that implements a 4-bit counter with load enable. The output "count" is a registered output, which means that it is updated only on clock edges. The input "clk" is the clock input, "load" is the load enable input, and "data" is the input data to load into the counter.
The "always @(posedge clk)" block is a sequential logic block that updates the "count" output based on the clock and load signals. If the "load" signal is high, then the counter is loaded with the value of "data". Otherwise, on every positive edge of the clock, the counter increments by 1.
Note that this Verilog code assumes that the "count" output, the "clk" and "load" inputs, and the "data" input are all 1-bit signals. If you want to use multi-bit signals, you would need to modify the code accordingly. Additionally, this code implements a rising-edge triggered counter. If you wanted to implement a falling-edge triggered counter, you would need to modify the code accordingly.